Hanson Liu

← Hardware projects

Hardware project

AC Ripple-Injection Lab Board

Analog Devices

During my time at ADI as an Applications Engineering Intern for the HP Team, along with a lot of lab work that involved power-regulator characterization, I was also tasked with the project of developing a ripple injection PCB!

Based on Application Note AN-159, the board's goal is to inject a controlled AC ripple on top of a DC voltage, so a power-regulator's ability to reject that ripple (PSRR) can be characterized on the bench. The project entailed finding new SMD components to replace original THT copper-plate design then doing all the component routing in Cadence Allegro. The new revision was verified in LTspice with each new component's respective modeling imported to confirm it still functioned and was still closed-loop stable.

Thanks to my mentor, we were able to finish the board before my internship finished! Towards the last couple weeks of my internship, I got to personally use the board to characterize the PSRR of several ADI/LT LDOs, as well as the Silent Switcher 3 Buck Regulators, across a range of current-loading conditions.

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Hardware project

Minecraft Jukebox

Project in a Box · UC San Diego

One of my favorite projects that I've led here at Project in a Box! I, along with my amazing team of technical leads, developed a fully functional life-size minecraft jukebox!

The project is fully coded in the Arduino IDE. It implements a RFID module to read RFID cards sandwiched inside the MC Jukebox discs, each card's ID maps to a specific track to be played. The music is implemented with a DFMini MP3 Player Module. After a card's ID is recognized, the DAC outputs of the MP3 module are then fed into a audio amplifier and Sallen-Key bandpass filtering signal chain, optimized for a clean listening experience!

I designed the chassis of the MC jukebox in Onshape CAD, in which each wall is made of lasercut plywood to emulate the original video game's design. I personally suck at painting though, so I'd like to thank the PiB media team and my good friend Madeline Fruin for helping out with painting the jukebox and the custom discs! You guys are amazing!

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Hardware project

Screaming Plant

← Integrated circuit projects

Integrated circuit project

A Unit-Via Based Delta-Length SAR ADC

TSMC 65nm · full-custom schematic design and layout · Taped Out July 2026!

The design was completed as part of a "layout"-focused course ECE 266A, offered by Professor Drew Hall. In this course, a barebones 9-bit SAR ADC is already designed for us, and we are tasked with doing the layout in TSMC65nm using advanced layout techniques, such as common-centroid and interdigitation.

The reason why I described the class as "layout" focused, is because the option to do "extensions" is offered to students who desire a bit more challenge than others. My partner, Eamon Lee, and I, chose to do THREE EXTENSIONS! Thats right, you read it correctly, THREE!

Here are the notable changes to the original design that we took on:

1. Delta-Length-based CDAC using a Unit-Via approach — based on the 2018 IEEE paper “A Compact 10-b SAR ADC With Unit-Length Capacitors and a Passive FIR Filter” by Professor Pieter Harpe.
2. Monotonic Top-Plate Sampling switching scheme — based on the 2010 IEEE paper “A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure” by C.-C. Liu et al.
3. Bootstrapped sampling switches with Deep N-Well devices for top-plate sampling.

Rather than building the SAR ADC's binary weighted capacitor bank using traiditonal MOM/MIM capacitors, our SAR ADC's CDAC is built using "Delta-Caps". It is well know that we can change the capacitance of a metal strip by scaling the length. However, this does not guarantee a consistent and proportional relationship, as edge effects don't scale with length. So the premise of "Delta-Caps" can be described as this: What if we took two strips of metals, and drove one strip with positive charge, and the other strip with negative charge? From here, you can consistently account for edge effects with subtraction, and create a consistent unit capacitance by scaling the DIFFERENCE in length between the two!

However, designing a SAR ADC using these Delta-Caps comes at a nasty price. Our unit Delta-Cap had a capacitance of roughly ~280aF. Thats ATTO, not even femto! That is insanely small! Having a capacitance this small, required us to do all the additional extensions to make the Delta-Dac SAR even functional, since now we have to worry about kT/C noise...attenuation from the input capacitance of our comparator... high impedance switches driving the delta-cap strips ... it was a total nightmare!

Because of aforementioned design challenges, my partner and I sought to find ways to get the Delta-Dac SAR to just perform at a respectable level while still maintaining the incredibly compact sizing that comes with the Delta-Dac design. In the end, we were able to implement top-plate sampling, in which the outer ring laterally surrounding the delta strips were driven by boot-strapped switches for improved linearity and charge injection. Because of the incredibly small capacitances of the delta-strips, custom inverter switches were designed for each specific sized strip so optimal drive-strength can be achieved.

We also elected to implement a monotonic switching algorithm. Initially, we were concerned that common-mode (VCM) switching would connect the delta-strip capacitors to a potentially high-impedance source, degrading ADC performance. Although we later determined that VCM would be provided by a low-impedance source off-chip, we continued with monotonic switching due to its potential to reduce switching power and noise (and why not try something new!). While the resulting design achieved the lowest power consumption in the class, further reductions may have been possible with a PMOS-input comparator. Unfortunately, due to time constraints, we could not explore this by the tape-out deadline.

Without further ado, here is the final performance of our SAR ADC, post extraction:

← Integrated circuit projects

Integrated circuit project

PAM2 / PAM4 Voltage-Mode Hybrid Transmitter

TSMC 65nm · SerDes wireline transmitter

For more information, feel free to read my report.

In this project, we were tasked with designing a high-speed wireline transmitter driving an actual noisy channel characterized by physically measured S-parameters. The design specification required, at minimum, a voltage-mode transmitter on a ≥ 1 V supply, and that the signal clear a minimum RX eye at the receiver — an eye aperture of 0.3 UI and an eye height of 20 mV_ppd, both at a BER of 10⁻¹² under additive noise (σ = 5 mV_rms) and jitter (σ = 0.035 UI_rms).

In a great pursuit to push the data-rate as HIGH as possible, my partners and I were keen on implementing some form of swing-enhancement to open our RX eye as much as we can. After some literature review, we elected to implement a hybrid transmitter design inspired from the IEEE paper “A High-Swing 45 Gb/s Hybrid Voltage and Current-Mode PAM-4 Transmitter in 28 nm CMOS FDSOI” by M. Bassi et al. , which features both a source-series terminated driver, and a auxiliary push-pull current-mode driver. To allow for even further current injection from the current-mode driver, we also designed high-speed level shifters so that our entire design can be implemented with a larger supply.

After equalization, our design was able to reach a max simulated data-rate of 18Gbps, while still clearing the RX noise and jitter spec! Yahoo!

We were also able to implement the hybrid transmitter in PAM4! However, due to the nonlinear aspect of PAM4, we optimized the design to meet the provided eye height spec, as meeting the jitter spec was close to impossible. After equalization, we were able to achieve a max data-rate of 20Gbps! Holy Moly!

Below is the final summary of our driver's performance.

← Integrated circuit projects

Integrated circuit project

Ultra Low-Power ECG Instrumentation Amplifier

IBM 180nm · Biomedical ECG front-end

For more information, feel free to read my report.

The presented front-end amplifier design was developed for my final project for ECE203: Biomedical Integrated Circuits, taught by Professor Patrick Mercier. I designed an ECG amplifier that employs driven-right-leg (DRL) feedback to reduce the effects of common-mode 60Hz interference coupled in from the body. The design had to clear a baseline performance for specs relating to Mid-band Gain, CMRR, power consumption, input-referred noise, etc. Extra credit is rewarded to those who were able to push to even lower noise or lower power while keeping all other metrics iso-performance to spec.

I was able to achieve a nominal-consumption of only 667nW (yes haha funny number) and 2.7µVrms input-referred noise. My design was recognized as one of the top-performing submissions in my class, and I ended up receiving the top score in the class! Yay!

Below is the performance summary of the ECG amplifier in the nominal corner.

← Integrated circuit projects

Integrated circuit project

Folded-Cascode OTA

IBM 180nm · Two-stage folded-cascode op-amp

For more information, feel free to read my report.

The following Op-Amp design was assigned as a final project for the upper divisional course ECE164, taught by Professor Drew Hall. For this project, everyone is given the same Op-Amp design, but the sizings are entirely determined by the students.

In this project, my partner and I elected to approach the sizings with a gm/ID approach much akin to the one taught in the textbook "The gm/ID Methodology, a sizing tool for low-voltage analog CMOS Circuits" taught by Professors Paul Jespers and Boris Murmann (Murmann actually gave a seminar on this recently! You can even find the video on youtube!).

Although the design methodology of gm/ID can be applied in many different ways, here is how we used it for this project:

1. First choose a general, but well informed, value of gm/ID for your transistor. As an example, a gm/ID of 13 for our input pair devices was the best value possible given the minimum overdrive voltage constraint. This allows us to maximize our gain while also enabling our design to be fast enough to meet the bandwidth specs.
2. From here, we used a "square-law" approximation script in matlab to determine the approximate transconductance for a chosen value for gm/ID. This naturally instantly gives us the current, which we can then find the sizings for using provided Id/W look-up tables.
3. A similar approach can be used to solve for sizings based off of an expecation for current. As an example, the telescopic stage is not the primary contributor to the dominant and non-dominant poles, and thus it is in our best interest to have less current across them for the sake of intrinsic gain. A similar approach to 2. can now be approached to solve for r_o using gm/r_o look-up tables and a specificed value for current.

Using our gm/ID approach, we were able to have a great starting point for our circuit. From there a lot of iterative optimization is done to push the overal current down while still meeting spec.

Our design performed so well, we actually got chosen to present to Apple Cohorts during an end of the quarter competition! Unfortunately, out of the four groups that got selected to present, we placed fourth LOL. Shit happens. Still incredibly proud of what we've were able to accomplish, nonetheless!

Here's a summary of our op-amps performance!

← Integrated circuit projects

Integrated circuit project

8-Bit Carry-Less Adder

Custom PDK · 8-bit parallel-prefix Ling carry adder

For more information, feel free to read my report.